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Radical differences in electrical signaling and bus protocol require the use of a different mechanical form factor and expansion connectors (and thus, new motherboards and new adapter boards); PCI slots and PCI Express slots are not interchangeable.

The work of packetizing and de-packetizing data and status-message traffic is handled by the transaction layer of the PCI Express port (described later).

This allows the PCI Express bus to serve both cost-sensitive applications where high throughput is not needed, as well as performance-critical applications such as 3D graphics, networking (10 Gigabit Ethernet or multiport Gigabit Ethernet), and enterprise storage (SAS or Fibre Channel).

As a point of reference, a PCI-X (133 MHz 64-bit) device and a PCI Express 1.0 device using four lanes (×4) have roughly the same peak single-direction transfer rate of 1064 MB/s.

The PCI Express link between two devices can consist of anywhere from one to 32 lanes.

In a multi-lane link, the packet data is striped across lanes, and peak data throughput scales with the overall link width.

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